1. Field of the Invention
The present invention relates to a switching-type, inductive DC—DC converter with improved efficiency.
2. Description of the Related Art
As is known, switching-type, inductive DC—DC converters having a Boost or Buck-Boost circuit topology generate high voltages, of some hundreds of Volts, from relatively low input voltages, of only a few Volts, using inductive type components, the loading and unloading whereof are controlled by active components including control transistors switching on and off.
For a more detailed discussion of switching-type, inductive DC—DC converters of a flyback or boost type, see for example J. G. Kassakian, M. F. Schlecht, G. C. Verghese “Principles of Power Electronics,” Addison Wesley.
On this topic, FIG. 1 shows the basic circuit diagram of a switching-type, inductive DC—DC converter having a Boost type circuit topology.
As illustrated in FIG. 1, the DC—DC converter, indicated as a whole at 1, comprises an inductor 2, a control transistor 4 of NMOS type, a diode 6 and a capacitor 8.
In particular, the inductor 2 has a first terminal connected to a supply line 10 at a supply voltage VA, and a second terminal connected to a drain terminal of the control transistor 4, which has a source terminal connected to a ground line 12 at a ground voltage VGND, and a gate terminal receiving a control signal C.
The second terminal of the inductor 2, jointly with the drain terminal of the control transistor 4, forms an intermediate node 14 set at an intermediate voltage VI, the value whereof is correlated to the inductance of the inductor 2 and to the current flowing in the inductor 2.
The diode 6 has an anode terminal connected to the intermediate node 14 and a cathode terminal connected to a first terminal of the capacitor 8, the second terminal whereof is connected to the ground line 12.
The cathode terminal of the diode 6, jointly with the first terminal of the capacitor 8, forms an output node 16 of the DC—DC converter 1 and supplies an output voltage VH higher than the supply voltage VA.
In short, the control transistor 4 is switched on/off at a predetermined frequency, called switching frequency; when the control transistor 4 is on, a current flows between the supply line 10 and the ground line 12 through the inductor 2, that stores an electric energy correlated to the on-interval of the control transistor 4; instead, when the control transistor 4 is off, a current flows between the inductor 2, the diode 6 and the capacitor 8, so the electric energy stored in the inductor 2 is transferred to the capacitor 8, apart from any leaks.
Moreover, before the control transistor 4 can switch off, there must be sufficient electric energy stored in the inductor 2 to load the equivalent stray capacitance “seen” by the intermediate node 14 to a value such as to bring the voltage VI of the intermediate node 14, and therefore the output voltage VH, to the desired value VO. In mathematical terms, this can be represented by the following inequality:                                           1            2                    ⁢                      C            P                    ⁢                      V            0            2                          ≤                              1            2                    ⁢          L          ⁢                                           ⁢                      I            2                                              (        1        )            wherein I is the current flowing in the inductor 2 when the control transistor 4 is on, CP is the equivalent stray capacitance “seen” by the intermediate node 14, the first term of the inequality represents the electric energy necessary to load the equivalent stray capacitance CP and the second term of the inequality represents the electric energy stored in the inductor 2.
As may be noted from the above inequality, in order to obtain output voltages VH of some hundreds of Volts it is necessary to make a decidedly high electric current run in the inductor 2, easily of some Amps, which consequently generates a series of problems, well known to the skilled person, the solution of which involves considerable difficulties at planning and circuit level.
Besides the problems deriving from the high value of the currents involved, switching-type, inductive DC—DC converters of the type described above have the further drawback of being able to supply only one boosted voltage, so that, when numerous different boosted voltages are required, it is necessary to resort to many distinct inductors or to inductors with many windings, one for each boosted voltage that is needed, and this involves a considerable occupation of area.
Similar problems can also be found in switching-type, inductive DC—DC converters having a circuit topology of the Buck-Boost type, which differ from Boost type ones essentially in that the positions of the inductor and of the control transistor are exchanged, that is the inductor is connected to the ground line while the control transistor is connected to the supply line.
Another prior art switching-type, inductive DC—DC converter is shown in FIG. 2.
The DC—DC converter, indicated as a whole with 20, comprises an inductor 22, a control transistor 24, and a voltage multiplying or boosting circuit 25.
In particular, the inductor 22 has a first terminal connected to a supply line 30 at a supply voltage VA, and a second terminal connected to a drain terminal of the control transistor 24, which has a source terminal connected to a ground line 32 at a ground voltage VGND, and a gate terminal receiving a control signal C.
The second terminal of the inductor 22, jointly with the drain terminal of the control transistor 24, forms a first intermediate node 34 supplying an intermediate voltage VI, the value whereof is correlated to the inductance of the inductor 22 and to the current flowing in the inductor 22.
The voltage multiplying circuit 25 comprises three voltage multiplying stages of a capacitive type, cascade-connected and indicated respectively with 26.1, 26.2 and 26.3.
The voltage multiplying stages 26.1-26.3 have the same circuit structure and each comprise a boosting capacitor, indicated respectively 36.1, 36.2 and 36.3; a filtering capacitor indicated respectively 38.1, 38.2 and 38.3; and a first and a second diode, indicated 40.1, 40.2, 40.3 and, respectively, 42.1, 42.2, 42.3.
In particular, each boosting capacitor 36.1-36.3 has a first terminal connected to the intermediate node 34 and a second terminal connected to a second intermediate node, indicated respectively 44.1, 44.2, 44.3, connected to an anode terminal of the corresponding first diode 40.1-40.3 and a cathode terminal of the corresponding second diode 42.1-42.3.
The cathode terminal of each corresponding first diode 40.1-40.3 is connected to a first terminal of the respective filtering capacitor 38.1-38.3 and forms, jointly with it, an output node of the DC—DC converter 1, indicated respectively 46.1, 46.2, 46.3, supplying an output voltage, respectively VH1, VH2, VH3, and connected a to a respective load 50.1, 50.2, 50.3.
Moreover, the anode terminal of the second diode 42.1 of the first capacitive multiplying stage 26.1 is connected to the ground line 32; the anode terminal of the second diode 42.2 of the second capacitive multiplying stage 26.2 is connected to the output node 46.1 of the first capacitive multiplying stage 26.1; and the anode terminal of the second diode 42.3 of the third capacitive multiplying stage 26.3 is connected to the output node 46.2 of the second capacitive multiplying stage 26.2.
Lastly, the second terminal of the filtering capacitor 38.1 of the first capacitive multiplying stage 26.1 is connected to the ground line 32; the second terminal of the filtering capacitor 38.2 of the second capacitive multiplying stage 26.2 is connected either to the ground line 32 or to the output node 46.1 of the first capacitive multiplying stage 26.1, as schematically represented in FIG. 2 with a dashed line; and the second terminal of the filtering capacitor 38.3 of the third capacitive multiplying stage 26.3 is connected either to the ground line 32 or to the output node 46.2 of the second capacitive multiplying stage 26.2, as schematically represented in FIG. 2 with a dashed line.
The second terminals of the filtering capacitor 38.2, 38.3 of the second and of the third capacitive multiplying stage 26.2, 26.3 are connected either to the ground line 32 or to the output node 46.1, 46.2 of the first and, respectively, of the second capacitive multiplying stage 26.2, 26.3 depending on the particular application for which the DC—DC converter 20 is intended, as will be better explained below.
The operation of the DC—DC converter 20 is as follows.
The control transistor 24 is switched on and off at a pre-determined switching frequency; when the control transistor 24 is on, an electric energy correlated to the on-time of the control transistor 24 is stored in the inductor 22, while when the control transistor 24 is off, the electric energy stored in the inductor 22 is transferred to the filtering capacitors 38.1-38.3, except for any leaks, causing an increase of the voltage at the terminals.
In particular, since the anode terminals of the first diodes 42.2 and 42.3 of the second and the third capacitive multiplying stages 26.2, 26.3 are connected to the output node 46.1 of the first capacitive multiplying stage 26.1, and, respectively, to the output node 46.2 of the second capacitive multiplying stage 26.2, the voltage of the second intermediate node 44.2 depends not only on the intermediate voltage VI of the first intermediate node 34 but also on the voltage of the second intermediate node 44.1, just as the voltage of the third intermediate node 44.3 depends both on the intermediate voltage VI of the first intermediate node 34 and on the voltages of the second intermediate nodes 44.1 and 44.2.
In the DC—DC converter 20, therefore, the output voltage VH1 can reach at the most a value equal to the maximum value assumed by the intermediate voltage VI, the output voltage VH2 can reach a value equal to double the output voltage VH1, and the output voltage VH3 can reach a value equal to three times the output voltage VH1.
For example, by loading the inductor 22 so that the intermediate voltage VI has a value of 100 Volts, with the DC—DC converter 20 it is possible to obtain both an output voltage VH2 of 200 Volts and an output voltage VH3 of 300 Volts.
In general, with n voltage multiplying stages cascade-connected as described above and equal to each other, the maximum output voltage, that is the voltage on the output node of the n-th capacitive multiplying stage, is equal to n times the maximum value of the intermediate voltage VI.
While the output voltage remains the same (with respect to the DC—DC converters described previously with reference to FIG. 1), this allows the inequality (1) to be rewritten as follows:                                           1                          2              ⁢                              n                2                                              ⁢                      C            P                    ⁢                      V            0            2                          ≤                              1            2                    ⁢          L          ⁢                                           ⁢                      I            2                                              (        2        )            which, if solved for the variable I, shows how the electric current necessary to load the stray capacity CP associated with the first intermediate node 34 is reduced by a factor n with respect to that necessary in DC—DC converters without capacitive multipliers, with consequent significant reduction of the problems at planning and circuit level, initially described, deriving from the high value of the currents involved.
Moreover, if the filtering capacitors 38.2 and 38.3 are connected to the ground line 32, the voltage at their terminals is two times and, respectively, three times the intermediate voltage VI, while if they are connected to the output nodes 46.1 and, respectively, 46.2, the voltage at their terminals is equal to the intermediate voltage VI. Thereby the connection of these filtering capacitors to the output nodes of the preceding voltage multiplying stage allows a reduction by a factor n in the maximum voltage of the filtering capacitors, therefore less expensive manufacturing technologies may be used by virtue of the lower bulk and lower insulation problems.
The decision to connect the filtering capacitors to the ground line rather than to the output nodes of the preceding voltage multiplying stages in the cascade therefore depends on the application for which the DC—DC converter 20 is intended, in particular it depends on any limitations on the overall occupation of area on silicon on the DC—DC converter.
Although widely used, the output voltages VH1, VH2, VH3 may vary in a rather significant way when the loads 50.1, 50.2, 50.3 connected to the output nodes 46.1, 46.2, 46.3 vary.